Voltage controlled oscillators or voltage to frequency convertors, i.e. oscillators in which the output frequency is determined by the level of an input voltage are well known. Examples of such oscillator circuits are disclosed in U.S. Pat. No. 3,815,052 and in U.S. Pat. No. 3,911,378. In U.S. Pat. No. 3,815,052 a phase in the feedback loop of the oscillator is changed in response to the external control voltage, the change in phase causing a change in the oscillation frequency of the oscillator. Also in U.S. Pat. No. 3,911,378 the oscillation frequency is controlled by changing the phase shift in the feedback loop. In the circuit of that document the phase shift is governed by resistor-capacitor circuits, in which the capacitor is a reverse biased diode of which the capacitance is a function of the voltage across the diode.
In such a circuit the range over which the output frequency of the oscillator circuit can be adjusted is limited by the maximum range of the control voltage. Normally the control voltage is derived from the supply voltage of the circuit, which means that the level of the control voltage is delimited by the levels of said supply voltage. Supply voltages often cannot be chosen at will, as they are standardized to make circuits compatible and to allow the use of standard power supply units. For many digital circuits the voltage supply is standardized at 0 (Ground) and +5 Volts. Use of non-standard power supply units may involve substantial additional costs and the provision of additional supply leads will take up extra space on a printed circuit board.
Due to voltage drops in the control circuitry, the standardized supply voltages of 0 and 5 Volts results in a smaller range for the control voltage, the range may be reduced to about 0.5 to 4.5 Volts or even to 1 to 4 Volts. In a number of applications this range is considered insufficient to provide the adjustment of the frequency necessary in that specific application. For example, in a phase locked loop used to derive a clock signal from a digital data signal, frequency jumps may occur in the data signal. The phase locked loop must be able to follow those jumps and therefore it needs a certain capture range to be able to follow the frequency jumps.